Power-on reset circuits are usually required on various types of semiconductor integrated circuit chips to initialize various blocks of application circuit elements such as state machines and essential memory elements, for example, the memory gates of a non-volatile memory device. The semiconductor integrated circuit industry has developed various types of conventional power-on reset circuits for generating a power-on reset pulse in response to the application of a direct current (DC) common voltage V.sub.cc to the conventional power-on reset circuit. A typical conventional power-on reset circuit may be represented by a generic block diagram as shown in FIG. 1, with an input power supply voltage V.sub.cc applied to the conventional power-on reset circuit 2, which in response generates a power-on reset (PORST) pulse with a voltage roughly proportional to the input voltage V.sub.cc over a predetermined range of input power supply voltages.
When the integrated circuit is turned on, that is, when the supply voltage V.sub.cc increases from 0 V to a DC supply voltage V.sub.cc (DC), it is desirable that the voltage of the power-on reset pulse follow the supply voltage V.sub.cc exactly, up to a predetermined upper threshold voltage level V.sub.cc ', which is a voltage slightly lower than the DC supply voltage V.sub.cc (DC). When the supply voltage V.sub.cc reaches above the upper threshold voltage V.sub.cc ', it is desirable that the power-on reset pulse terminate exactly when it reaches the voltage level V.sub.cc '. It is also desirable that the power-on reset pulse start as early as possible at a minimum turn-on voltage V.sub.cc .degree. after the supply voltage V.sub.cc increases above the ground voltage 0 V. It is further desirable that the operating voltage range of the power-on reset pulse between the minimum turn-on voltage V.sub.cc .degree. and the maximum pulse voltage V.sub.cc ' be as insensitive to temperature and process variations as possible. However, the operating voltage ranges of power-on reset pulses generated by conventional power-on reset circuits are usually sensitive to variations due to the processing technology of semiconductor devices and to variations in operating temperatures.
In low voltage applications, the noise of the supply voltage V.sub.cc may be appreciable compared to the DC supply voltage V.sub.cc (DC). In this situation, the maximum pulse voltage V.sub.cc ', which is the same as the upper threshold V.sub.cc ' of the supply voltage V.sub.cc, may be set at a voltage level slightly lower than the DC voltage V.sub.cc (DC) to take the noise voltage into the account. However, if the voltage V.sub.cc ' at the end of the power-on reset pulse is too low, the application circuit which is to be reset by the power-on reset circuit may not be initialized properly. On the other hand, if the voltage V.sub.cc ' is too close to the DC supply voltage V.sub.cc (DC), the voltage V.sub.cc ' may shift to a voltage level higher than the DC supply voltage V.sub.cc (DC) due to the sensitivities of V.sub.cc ' to temperature and process variations in a conventional power-on reset circuit. In either case, an application circuit to which the conventional power-on reset circuit is connected may not be able to function correctly because it is not properly initialized by the temperature and process sensitive power-on reset pulse generated by the conventional power-on reset circuit.
Therefore, there is a need for a power-on reset circuit that is able to generate a power-on reset pulse with an upper threshold voltage V.sub.cc ' that is highly insensitive to temperature and process variations, particularly in situations in which the power-on reset circuit is implemented for generating power-on reset pulses in low voltage applications.